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Every post you make in this thread that is not "its done" becomes a 2pt INT or STR bonus for Sun Quan.
:P
Oh, I will note that I did have to buy food twice up until Cao Cao. A mix of not knowing where to go, a lot of long hikes from start to yellow scarves trouncing, and quite possibly early Li Su soldiers made things a bit hungry :P
PS
After having played RoLB and RoI … I really do miss quirkly lil sayings by different shop keeps and stuff. I *STILL* have wakey wakey eggs and bakey in my head…..
I fetched this from the download page rather than page 1.
I didn't power level or anything, and took out Ding Yuan before doing the gate to the east and approaching it 'correctly' (ie: I did Ding Yuan and then the Eunichs). This will be a restart for me, then. Don't get me wrong, I'm enjoying the character selection for the party (and it's weird but viable), but that 255 would come in handy… and after an hour or so…. spotted that one tile forest gap near the start, it won't be so bad (yeah, was wandering around a bit aimlessly to the south trying to figure out what to do heh). Will still do the Gold Key cave relatively early, Li Su is all too handy, as is $$ for a couple clubs ;).
Ran across Cao Cao / Cao Hong gate and decided it was a stopping point after losing. He still has Yan Re. Is he supposed to ? Or do I start afresh with page1 download ?
bank switching on a processor that doesn't natively support it or something is a PITA yes
ideally, depending if it the bank switch isn't costly (it doesn't look to be), the ISR's in all but one of the banks would need to push the current bank (or store it somewhere), switch to the bank that has the real ISR, and jump to it…. how ya do the wrappers between isr strapping to the real isr would be entirely up to you, but the real ISR would still need to switch back to the appropriate bank and rti. so…. the wrapper code would prolly need to be in each bank…. and yeah, i know – all at same addresses heh.
Quote:NMI (Non-Maskable Interrupt) is the type of interrupt generated by the PPU when V-Blank
occurs at the end of each frame. NMIs are not affected by the interrupt disable bit in the
status register, so execution is always interrupted when they occur [31]. However, triggering
of a NMI can be prevented if bit 7 of PPU Control Register 1 ($2000) is clear. When a NMI
occurs the system jumps to the address located at $FFFA and $FFFB. The handling of NMIs
is shown in figure 2-4.
And then looking at a schematic:
http://nesdev.com/Ntd_8bit.jpg
CPU NMI is a direct connect to the PPU.
Soooo the above quote is undoubtedly correct.
gamers go to there to either broadcast themselves playing games or watch other folks play games. twitch.tv
…. do you have a free byte somewhere?
do you have space to store which page you're on in it ?
can you set up the ISR to do this page switch before all of the pulls and iret ? (page, pull pull pull iret) ?
i'm… not entirely sure how nes memory mappers work, not entirely sure blah blah blah….
but… i imagine my suggestion aint easily feasible due to working with binaries rather than source .. thus no room to squeeze instructions into…
the ee79 is the interrupt address vector the processor will jump to handle NMI interrupts. if you replaced fffa/fffab with something other than ee79, it'd jump there instead.
looking at 6502 docs, the isr setup stuff internal to the processor does PHP already. dunno if nes 6502 is the same… but… this would make the php's at the start of each ISR pointless?
Given that it's an ISR, given that the ISR appears to push / pull a bit on the stack on it's own (and who knows how much the sub routines do) …
what happens in 6502 if you try to push too much on the stack ? what happens to the stack pointer / counter / whatever the fuck 6502 calls it ? heh.
with the new code that's been written, is it possible that in rare circumstances that a fair amount of stuff has been pushed on to the stack by new code…. then while the stack is kinda full an INT triggers… and the stack gets overflowed or something ?
in your traces, keep an eye on the stack pointer basically on a crash replay ?
Dunno how 6502 code is typically written.. but 8051 and other stuff… there's a dedicated block of code near the front of the ROM that has the interrupt entry points. They typically only exist as a 'long jump interrupt_handler0/1/2/whatever' kind of instruction. And each of the front-of-rom entry points are typically only long enough to include this immediate jmp spring board.
Of course, why on god's green earth would an ISR push things and not restore them properly is a bit beyond me.
My only possible guess would be if somehow there was an instruction timing thing going on …. where…. designers knew that every X often, an interrupt triggers and does stuff. Thus they designed their code so that each block of shit they were doing would finish within X amount of time and be kinda idle waiting for it to occur. But that makes little sense really. I dunno if I've ever seen DoaE ever have lag problems, but it just aint sane.
If ya look further down from EE79… it looks like it does ISR style stuff… pushes registers … does a bunch of stuff… then:
0F:EF2D:68 PLA
0F:EF2E:20 AA C4 JSR $C4AA
0F:EF31:68 PLA
0F:EF32:A8 TAY
0F:EF33:68 PLA
0F:EF34:AA TAX
0F:EF35:68 PLA
0F:EF36:28 PLP
0F:EF37:40 RTI
pops all those registers and RTI (return from interrupt).
i've not looked at the register push and pop (pull? sorry, silly 6502 nomenclature) to make sure it's correct… but …. assuming the last PLA is correct…. A should have been reset to what whatever it was supposed to be.
I'm not entirely sure what this ISR does, it's got a few 'gosubs' within it… which would be more pushing/popping…
Not a 6502 programmer, but doing a quick bit of reading and look at what ya got…
Is the PC reg truly jumping to EE79 in the traces ?
Cause… the only way I can possibly see that ever happening is an interrupt or similar.
$84BE:A9 01 LDA #$01 A:00 X:D5 Y:00 S:12 P:nvUBdIZc
$84C0:C5 CE CMP $00CE = #$02 A:01 X:D5 Y:00 S:12 P:nvUBdIzc
$84C2:D0 19 BNE $84DD A:01 X:D5 Y:00 S:12 P:NvUBdIzc
LDA doesnt write to memory any and doesn't write to the PC
CMP is a read instruction changing SR but still readonly…
The addressing on BNE is relative, no ? So…. you can't go from 8xxx to Exxx from a single byte.
$86BD:B1 CC LDA ($CC),Y @ $0762 = #$00 A:00 X:0A Y:05 S:10 P:nvUBdIzc
There is zero way this could effect the PC out of normal ? Loading from mem to A shouldn't affect a damn thing.
$8260:4A LSR A:00 X:00 Y:1D S:1E P:nvUBdIZc
$8261:90 03 BCC $8266 A:00 X:00 Y:1D S:1E P:nvUBdIZc
LSR / 4A = just an A shift….
BCC is also relative and can't get to Exxx in a single byte (8xxx -> Exxx).
EE79 being PHP really seems to hint it's an IRQ or interrupt or something.
Quote:Unfortunately not being able to play it on twitch you wont be able to simply spectate lol.For FOW, I can prolly switch to playing from my primary desktop, which would be friendly for streaming to twitch (this netbook just doesn't quite have enough oomf). Note that I'm not particularly speedy when playing the game, so it'd prolly be a boring ass watch ;).
Busy with real life, playing a bit of RoI, playing a bit of vanilla DoaE, la la la ….
BTW – Welcome back! <3
